1. Field of the Invention
The invention relates to a high-speed output transconductance amplifier (OTA), which configures a cross-coupled circuit with programmable switches to offer a high-speed receiver capable of operating at different voltage levels.
2. Description of Related Art
An application example of a typical output transconductance amplifier (OTA) in an existing high speed receiver is given as follows.
FIG. 1 is a circuit diagram of a typical OTA 10. In FIG. 1, the OTA 10 is formed by an NMOS current mirror circuit M1-M2, two PMOS current mirror circuits M3-M4, M5-M6 and a differential operational amplifier M7-M9. As shown in FIG. 1, the NMOS current mirror circuit includes NMOS transistors M1-M2 with common gates and common grounding sources, wherein a drain of transistors M1 is connected to the common gate providing a current mirror function. The NMOS transistor M9 acts as a current source providing a reference current IABC controlled by a differential voltage pair REF, IN respectively connected to gates of transistors M8, M7. Thus, DC power dissipation from output-to-input thermal feedback (because in the layout, transistors M7 and M8 are placed next to transistors M2 and M3) is decreased by adjusting the reference current through input voltages of REF, IN. Additionally, the symmetric diode configuration of transistors M4 and M5 in parallel respectively with transistors M3 and M6 is a voltage to current converter and sends the current through transistors M3 and M6. In this diode configuration, it can keep transistors M7 and M8 saturated and provide a high resistance region in the middle for transistors M3 and M6 so the output switches faster to minimize delay. The OTA is a current steering circuit with an output current Io. The output current Io can be represented by the differential input voltages IN, REF:
Io=gm(INxe2x88x92REF)
where, gm is the transconductance gain equal to IABC/2VT, and VT is the threshold voltage of an MOS device.
However, although this OTA 10 can provide suitable current to ensure function correctly (e.g. using a 3.3V device in an SSTL-3, 3.3V system), but for a lower voltage system (e.g. using a 3.3V device in an SSTL-2, 2.5V system), it will not operate to function correctly. This is because the differential pair M7 and M8 may limit the output signal range and increase the susceptibility to device mismatching due to square-law behavior of a device in saturation. Further, a current mirror ratio B has to decrease in order to reach the requested gain gm (see MARC G. R. DEGRAUWE and WILLY M. C. SANSEN, xe2x80x9cThe Current Efficiency of MOS Transconductance Amplifiers,xe2x80x9d IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 3, June 1984.)
Accordingly, an object of the invention is providing a high-speed output transconductance amplifier capable of operating at different voltage levels by means of switching on or off the extra cross-coupled circuit.
The invention provides a high-speed output transconductance amplifier capable of operating at different voltage levels, including an NMOS current mirror circuit consisting of a first NMOS transistor with a drain, a gate and a diode-configured NMOS with a drain and a gate connected to the gate of the first NMOS and the drain of the diode-configured NMOS transistor; two PMOS current mirror circuits consisting of a first PMOS transistor with a gate and a drain connected to the drain of the first NMOS transistor to form a connection point as an output terminal, a second PMOS transistor with a gate and a drain connected to the drain of the diode-configured NMOS transistor, a first diode-configured PMOS transistor with a drain and a gate connecting the drain of the first diode-configured PMOS transistor and the gate of the first PMOS transistor, and a second diode-configured PMOS transistor with a drain and a gate connected to the drain of the second diode-configured PMOS transistor and the gate of the second PMOS transistor; a cross-coupled circuit consisting of a first cross-coupled unit having a first programmable switch and a third PMOS transistor connected in parallel to the first diode-configured PMOS transistor, with a gate connected to the first switch, and a second cross-coupled unit having a second programmable switch and a fourth PMOS transistor connected in parallel to the second diode-configured PMOS transistor, with a gate connected to the second switch; and a differential operational amplifier consisting of a second NMOS transistor with a drain connected to the first switch and the drain of the second diode-configured PMOS transistor, a gate connected to a first voltage, and a source, a third NMOS transistor with a drain connected the second switch and the drain of the first diode-configured PMOS transistor, a gate connected to a second voltage, and a source, and a fourth NMOS transistor with a drain connected to the sources of the second and third NMOS transistors and a gate connected to a third voltage, wherein the fourth NMOS transistor, the third NMOS transistor, and the first diode-configured NMOS transistor respectively are grounded, and all PMOS transistors respectively have a source connected to an external voltage.